1. Field of the Invention
The present invention relates generally to highly-integrated semiconductor memory devices, and more particularly to a dynamic random-access memory incorporating therein a peripheral circuit arrangement that generates a potentially raised or boosted voltage for use in word-line drive operations.
2. Description of the Related Art
Semiconductor dynamic random-access memory (DRAM) devices using MOS transistors are becoming more widely used in the manufacture of digital computer systems, as the speed and cost advantages of these devices increase. The cost per bit of storage using RAMs has decreased as the number of bits or memory cells per package increases. As the number of bits increases, the memory cell size decreases while a chip substrate size is gradually expanded, thereby to attain a higher packing density thereon. This causes signal transmission on word lines associated with the memory cells to undesirably decrease due to an increase in the resistance of the word lines and inherent parasitic capacitance thereof on enlarged chip substrate. This factor degrades the performance of the MOS-DRAMS: the speed of data-access operations.
There is a trade-off between the packing density and the data-access speed in such DRAMs. As DRAMs require higher packing density and higher speed, the booster circuit for providing the word lines with a drive signal of potential-raised potential becomes more critical. Conventionally, the booster circuit serves to supply the drive signal to a selected one of the word lines so as to enable a high voltage, representing a "1" bit of binary information, to be stored or "written" into a storage capacitor of a memory cell being selected. The word-line drive signal of boosted potential is generated once after a data-write address is designated externally; the word lines are typically deactivated and kept at the low potential level before the address is designated. It is only after the address establishment is done that the boosted drive voltage is allowed to be transferred to the selected word line via a pre-decoder circuit and a wiring line of increased length. This results in the potential rise up to a required high potential level being delayed on the selected word line; in other words, the activated word line is "ramped" slowly toward the high potential level. It thus takes much time for the charge-up operation at the storage capacitor in a selected memory cell. The high-speed data access operations of DRAMs cannot be expected.